1. Technical Field
The present invention relates to a design structure for switching a digital circuit clock net driver without losing clock pulses. More particularly, the present invention relates to a design structure for detecting clock edge alignments in order to select a clock signal from a plurality of clock signals without introducing clock cycle dead time.
2. Description of the Related Art
As technology advancements push digital circuit operating frequencies higher, an increase in power consumption and thus, heat generation, have grown to significant levels. Aggressive processor designs today use higher operating frequencies in order to deliver increased performance. A challenge found with these processor designs, however, is that they require a substantial amount of power and generate a substantial amount of heat. As a result, these designs face problems such as reduced battery life as well as undesirable noise levels from fans that are required to ventilate the processor.
One solution to reduce power consumption is to design a high-speed processor with the ability to control its own clock frequency and supply voltage. This is known as “dynamic voltage scaling,” or DVS, a technique that varies the supply voltage and clock frequency based on processor computation load. By this approach, during intervals when the processor demands are low, both frequency and voltage are scaled down. Conversely, during intensive processor computations, frequency and voltage are switched to a maximum level.
One approach to switching clock frequencies is to have multiple clock drivers running at different frequencies that are selected through a glitchless multiplexer. The different clock drivers are driven from the same source phase-locked loop (PLL) where the varying frequencies are achieved by ratioed frequency dividers. It is even possible to have programmable dividers that provide a range of operating frequencies. A challenge found, however, is that changing the frequencies on these dividers can introduce glitches on the clock multiplexer output.
Existing art may use a multiplexer (mux) to prevent clock glitches from reaching device circuitry. The glitchless multiplexer selects between multiple input clock sources and transitions between sources glitchlessly. A challenge found with current glitchless multiplexer designs, however, is that they ensure glitchless operation by removing clock pulses and holding the clock net output stable for an extended period of time before the multiplexer outputs the new clock.
While this may prevent glitches, this solution creates clock cycle “dead time” that presents problems in other areas, such as with dynamic circuits expecting a certain clock period. For example, the state of a given circuit depends on a capacitive charge. If the clock period is too long, the dynamic circuit's capacitive charge is not refreshed and thus, state is lost due to leakage current. As such, when a glitchless multiplexer changes operating frequency, dynamic circuits may be adversely affected by its “dead time.”
Existing art attempts to alleviate this issue by using a reference clock to indicate when to change clock signals. The reference clock, however, operates at a lowest common multiple of the clock signals from which are selected. A challenge found with this approach is that possible combinations of clock ratios that may be switched are limited by the frequency of the lowest common multiple clock.
What is needed, therefore, is a system and method that provides clock switching ratio flexibility to dynamically switch clock signals without introducing clock cycle dead time into a device's circuitry.